FIG. 1 is a cross-sectional view of a portion of a prior art insulated gate turn-off thyristor 10 (IGTO) described in U.S. Pat. No. 7,705,368, incorporated herein by reference. An NPNP semiconductor layered structure is formed. In FIG. 1, there is a PNP transistor formed by a p+ substrate 12, an n− epitaxial (epi) layer 14, and a p-well 16. There is also an NPN transistor formed by the layer 14, the p-well 16, and an n+ layer 18. A bottom anode electrode 20 contacts the substrate 12, and a top cathode electrode 22 contacts the n+ layer 18. Trenches 24, coated with an oxide layer 25, contain a conductive gate material 26 (forming interconnected vertical gate regions) which is contacted by a gate electrode 28. The p-well 16 surrounds the gate structure, and the n− epi layer 14 extends to the surface around the p-well 16.
When the anode electrode 20 is forward biased with respect to the cathode electrode 22, but without a sufficiently positive gate bias, there is no current flow, since the product of the betas (gains) of the PNP and NPN transistors is less than one.
When there is a sufficient positive voltage applied to the gate, and there is a sufficient anode-cathode voltage, electrons from the n+ layer 18 become the majority carriers along the sidewalls and below the bottom of the trenches 24 in an inversion layer, causing the effective width of the NPN base (the portion of the p-well 16 below the trenches 24) to be reduced. As a result, the beta of the NPN transistor increases to cause the product of the betas to exceed one. This results in “breakover,” when holes are injected into the lightly doped n− epi layer 14 and electrons are injected into the p-well 16 to fully turn on the thyristor. This is a controlled latch-up of the device. Accordingly, the gate bias initiates the turn-on, and the full turn-on is accomplished by the current flow through the NPN and PNP transistors.
When the gate bias is removed, the thyristor turns off.
Although not described in U.S. Pat. No. 7,705,368, the identical gate and cathode structure shown in FIG. 1 may be repeated as an array of cells across the thyristor, and the various components may be connected in parallel so each cell conducts a small portion of the total current. The array (or matrix) of cells includes cells designed to be inner cells and cells designed to be edge cells proximate to the edge of the p-well 16.
FIG. 2 is a cross-section of a portion of an edge cell 32 of a thyristor described in Applicant's U.S. patent publication US 2013/0115739, incorporated herein by reference, filed on Oct. 10, 2012 and published on May 9, 2013. The principle of operation of the cell 32 is the same as that of FIG. 1. The edge cell 32 includes a p-well 36, insulated gate regions 38, an oxide layer 39 within the trenches, an n+ layer 40 between the gate regions 38, a cathode electrode 42, a gate electrode 44, and dielectric regions 46 patterned to insulate the metal from certain areas. The cells are formed in an n− epi layer 50 grown over a silicon p+ substrate 52. An anode electrode 54 contacts the substrate 52.
The thyristor is formed of both inner cells and edge cells connected in parallel in a two-dimensional matrix.
As shown in FIG. 2, the edge cells, unlike the “inner” cells, are next to p+ guard rings 57 and 58 formed in the n− epi layer 50, which reduce electric field crowding near the edges of the die to improve the breakdown voltage of the thyristor.
Such IGTO thyristors have a relatively high current density when on. In contrast, insulated gate bipolar transistors (IGBTs) generally have a lower current density when on. Accordingly, for at least high current applications, IGTO thyristors are preferred.
A drawback of the IGTO thyristor of FIG. 1 or 2 is a fairly high gate turn-on voltage in conjunction with the difficulty of fabricating IGTO's with a consistent turn-on voltage. This lack of reproducibility is due to the difficulty is achieving precise gate trench depths, the difficulty in achieving precise doping levels, the difficulty is achieving the target gains of the NPN and PNP transistors, and other factors. Thus, the gate voltage for sufficiently modulating the NPN transistor base width to cause the product of the gains to exceed one (to initiate the thyristor action) is difficult to reproduce from one lot of IGTO thyristors to another.
What is needed is an improvement of the IGTO thyristor shown in FIG. 1 or 2 to lower the gate threshold voltage for turning on the thyristor and to make the turn-on voltage more consistent from one lot of thyristors to another.